ATMEGA32-16PU Atmel, ATMEGA32-16PU Datasheet - Page 205
![IC AVR MCU 32K 16MHZ 5V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA32-16PU
Manufacturer Part Number
ATMEGA32-16PU
Description
IC AVR MCU 32K 16MHZ 5V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA32L-8AU.pdf
(21 pages)
2.ATMEGA32L-8AU.pdf
(346 pages)
3.ATMEGA32-16PU.pdf
(345 pages)
Specifications of ATMEGA32-16PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
32
Interface
2-Wire/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
4.5-5.5 V
Data Rom Size
1024 B
Height
4.83 mm
Length
52.58 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Width
13.97 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1024Byte
Ram Memory Size
2KB
Rohs Compliant
Yes
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32-16PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 205 of 345
- Download datasheet (3Mb)
Differential Gain Channels
Changing Channel or
Reference Selection
2503G–AVR–11/04
Table 81. ADC Conversion Time
When using differential gain channels, certain aspects of the conversion need to be
taken into consideration.
Differential conversions are synchronized to the internal clock CK
ADC clock. This synchronization is done automatically by the ADC interface in such a
way that the sample-and-hold occurs at a specific phase of CK
ated by the user (i.e., all single conversions, and the first free running conversion) when
CK
clock cycles from the next prescaled clock cycle). A conversion initiated by the user
when CK
nism. In Free Running mode, a new conversion is initiated immediately after the
previous conversion completes, and since CK
started (i.e., all but the first) free running conversions will take 14 ADC clock cycles.
The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequen-
cies may be subjected to non-linear amplification. An external low-pass filter should be
used if the input signal contains higher frequency components than the gain stage band-
width. Note that the ADC clock frequency is independent of the gain stage bandwidth
limitation. For example, the ADC clock period may be 6 µs, allowing a channel to be
sampled at 12 kSPS, regardless of the bandwidth of this channel.
If differential gain channels are used and conversions are started by Auto Triggering, the
ADC must be switched off between conversions. When Auto Triggering is used, the
ADC prescaler is reset before the conversion is started. Since the gain stage is depen-
dent of a stable ADC clock prior to the conversion, this conversion will not be valid. By
disabling and then re-enabling the ADC between each conversion (writing ADEN in
ADCSRA to “0” then to “1”), only extended conversions are performed. The result from
the extended conversions will be valid. See “Prescaling and Conversion Timing” on
page 202 for timing details.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-
porary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the
conversion starts on the following rising ADC clock edge after ADSC is written. The user
is thus advised not to write new channel or reference selection values to ADMUX until
one ADC clock cycle after ADSC is written.
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
ADC2
is low will take the same amount of time as a single ended conversion (13 ADC
ADC2
is high will take 14 ADC clock cycles due to the synchronization mecha-
Sample & Hold (Cycles
from Start of
Conversion)
1.5/2.5
13.5
1.5
2
ADC2
is high at this time, all automatically
Conversion Time (Cycles)
ATmega32(L)
ADC2
ADC2
. A conversion initi-
13/14
equal to half the
13.5
25
13
205
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