ATMEGA32-16PU Atmel, ATMEGA32-16PU Datasheet - Page 98

• Manufacturer Part Number: ATMEGA32-16PU
• Description: IC AVR MCU 32K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 32
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 2KB
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

98
ATmega32(L)
Figure 46. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In
addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set
when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts
are enabled, the interrupt handler routine can be used for updating the TOP and com-
pare values.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the Compare Registers. If the TOP value is lower
than any of the Compare Registers, a compare match will never occur between the
TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining
the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is
changed to a low value when the counter is running with none or a low prescaler value,
there is a risk that the new ICR1 value written is lower than the current value of TCNT1.
The result will then be that the counter will miss the compare match at the TOP value.
The counter will then have to count to the MAX value (0xFFFF) and wrap around start-
ing at 0x0000 before the compare match can occur. The OCR1A Register however, is
double buffered. This feature allows the OCR1A I/O location to be written anytime.
When the OCR1A I/O location is written the value written will be put into the OCR1A
Buffer Register. The OCR1A Compare Register will then be updated with the value in
the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is
done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By
using ICR1, the OCR1A Register is free to be used for generating a PWM output on
OC1A. However, if the base PWM frequency is actively changed (by changing the TOP
value), using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1x1:0 to 3 (See Table 44 on
page 105). The actual OC1x value will only be visible on the port pin if the data direction
for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by
TCNTn
OCnx
OCnx
Period
1
2
3
4
5
6
7
8
OCRnx / TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
OCnA Interrupt Flag Set
(Interrupt on TOP)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
2503G–AVR–11/04