ATMEGA32-16PU Atmel, ATMEGA32-16PU Datasheet - Page 33

• Manufacturer Part Number: ATMEGA32-16PU
• Description: IC AVR MCU 32K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 32
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Data Rom Size: 1024 B
• Height: 4.83 mm
• Length: 52.58 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 13.97 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 2KB
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog Comparator
Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
JTAG Interface and On-chip
Debug System
2503G–AVR–11/04
When entering Idle mode, the Analog Comparator should be disabled if not used. When
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-
erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on
page 196 for details on how to configure the Analog Comparator.
If the Brown-out Detector is not needed in the application, this module should be turned
off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all
sleep modes, and hence, always consume power. In the deeper sleep modes, this will
contribute significantly to the total current consumption. Refer to “Brown-out Detection”
on page 37 for details on how to configure the Brown-out Detector.
The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-
tor, the Analog Comparator or the ADC. If these modules are disabled as described in
the sections above, the internal voltage reference will be disabled and it will not be con-
suming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be
used immediately. Refer to “Internal Voltage Reference” on page 39 for details on the
start-up time.
If the Watchdog Timer is not needed in the application, this module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Watchdog Timer” on page 39 for details on how
to configure the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power.
The most important thing is then to ensure that no pins drive resistive loads. In sleep
modes where the both the I/O clock (clk
input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to the section “Digital Input
Enable and Sleep Modes” on page 51 for details on which pins are enabled. If the input
buffer is enabled and the input signal is left floating or have an analog signal level close
to V
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power
down or Power save sleep mode, the main clock source remains enabled. In these
sleep modes, this will contribute significantly to the total current consumption. There are
three alternative ways to avoid this:
•
•
•
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP
controller is not shifting data. If the hardware connected to the TDO pin does not pull up
the logic level, power consumption will increase. Note that the TDI pin for the next
device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit
in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the
JTAG interface.
CC
Disable OCDEN Fuse.
Disable JTAGEN Fuse.
Write one to the JTD bit in MCUCSR.
/2, the input buffer will use excessive power.
I/O
) and the ADC clock (clk
ATmega32(L)
ADC
) are stopped, the
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