AT90USB646-MU Atmel, AT90USB646-MU Datasheet - Page 372

IC AVR MCU 64K 64QFN

AT90USB646-MU

Manufacturer Part Number
AT90USB646-MU
Description
IC AVR MCU 64K 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet

Specifications of AT90USB646-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
90USB
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, TWI, USART, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Cpu Family
AT90
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
4KB
# I/os (max)
48
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
QFN EP
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT90USB646-16MU
AT90USB646-16MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90USB646-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
29.6
29.6.1
29.6.2
29.6.3
372
Parallel Programming
AT90USB64/128
Enter Programming Mode
Considerations for Efficient Programming
Chip Erase
Table 29-12. No. of Words in a Page and No. of Pages in the EEPROM
The following algorithm puts the device in parallel programming mode:
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
The Chip Erase will erase the Flash and EEPROM
not reset until the program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note:
Load Command “Chip Erase”
1. Apply 4.5 - 5.5V between V
2. Set RESET to “0” and toggle XTAL1 at least six times.
3. Set the Prog_enable pins listed in
4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after
5. Wait at least 50 µs before sending a new command.
• The command needs only be loaded once when writing or reading multiple memory
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
• Address high byte needs only be loaded before programming or reading a new 256 word
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
locations.
EESAVE Fuse is programmed) and Flash after a Chip Erase.
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
100 ns.
+12V has been applied to RESET, will cause the device to fail entering programming
mode.
EEPROM Size
1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
1K bytes
2K bytes
4K bytes
Page Size
4 bytes
8 bytes
8 bytes
CC
and GND.
PCWORD
Table 29-8 on page 371
EEA[2:0]
EEA[2:0]
EEA[2:0]
(1)
memories plus Lock bits. The Lock bits are
Pages
No. of
256
256
512
EEA[10:3]
EEA[11:3]
to “0000” and wait at least
PCPAGE
EEA[9:3]
EEAMSB
10
11
9
7593K–AVR–11/09

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