P89V52X2FA,512 NXP Semiconductors, P89V52X2FA,512 Datasheet - Page 17

• Manufacturer Part Number: P89V52X2FA,512
• Description: IC 80C51 MCU FLASH 8K 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V52X2FA,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 44-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Eeprom Size: 192 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM11011 - BOARD FOR P89V52X2 44-TQFP622-1017 - BOARD 44-ZIF PLCC SOCKET622-1012 - BOARD FOR P89V52X2 44-TQFP622-1008 - BOARD FOR LPC9103 10-HVSON622-1002 - USB IN-CIRCUIT PROG LPC9XX
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4249-5; 935282528512; P89V52X2FA

NXP Semiconductors
P89V52X2_3
Product data sheet
6.8.1 Mode 0
6.8.2 Mode 1
Table 14.
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a fixed divide-by-32 prescaler.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the Special Function Register TCON
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See
Bit
3
2
1
0
Fig 10. Timer/Counter 0 or 1 in Mode 0 (13-bit counter)
INTn pin
TnGate
Tn pin
osc/6
TRn
TCON - Timer/Counter control register (address 88H) bit description
Symbol
IE1
IT1
IE0
IT0
Figure
11.
Rev. 03 — 4 May 2009
C/T = 0
C/T = 1
Description
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/LOW-level is detected. Cleared by hardware when the interrupt
is processed, or by software.
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/LOW-level that triggers external interrupt 1.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/LOW-level is detected. Cleared by hardware when the interrupt
is processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/LOW-level that triggers external interrupt 0.
80C51 with 256 B RAM, 192 B data EEPROM
control
Figure 10
(Figure
(5-bits)
TLn
shows Mode 0 operation.
8). The GATE bit is in the TMOD
(8-bits)
THn
Figure
overflow
10). There are two
P89V52X2
© NXP B.V. 2009. All rights reserved.
TFn
…continued
002aaa519
interrupt
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