P89V52X2FA,512 NXP Semiconductors, P89V52X2FA,512 Datasheet - Page 45

• Manufacturer Part Number: P89V52X2FA,512
• Description: IC 80C51 MCU FLASH 8K 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V52X2FA,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 44-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Eeprom Size: 192 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM11011 - BOARD FOR P89V52X2 44-TQFP622-1017 - BOARD 44-ZIF PLCC SOCKET622-1012 - BOARD FOR P89V52X2 44-TQFP622-1008 - BOARD FOR LPC9103 10-HVSON622-1002 - USB IN-CIRCUIT PROG LPC9XX
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4249-5; 935282528512; P89V52X2FA

NXP Semiconductors
9. Dynamic characteristics
Table 45.
Over operating conditions: load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF
T
[1]
P89V52X2_3
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
osc
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
PXAV
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
WHQX
QVWH
RLAZ
WHLH
amb
T
= 40 C to +85 C; V
cy(clk)
= 1/f
Parameter
oscillator frequency
ALE pulse width
address valid to ALE LOW time
address hold after ALE LOW time
ALE LOW to valid instruction in time
ALE LOW to PSEN LOW time
PSEN pulse width
PSEN LOW to valid instruction in time
input instruction hold after PSEN time
input instruction float after PSEN time
PSEN to address valid time
address to valid instruction in time
PSEN LOW to address float time
RD LOW pulse width
WR LOW pulse width
RD LOW to valid data in time
data hold after RD time
data float after RD time
ALE LOW to valid data in time
address to valid data in time
ALE LOW to RD or WR LOW time
address to RD or WR LOW time
data hold after WR time
data output valid to WR HIGH time
RD LOW to address float time
RD or WR HIGH to ALE HIGH time
Dynamic characteristics
osc
.
DD
= 2.7 V to 5.5 V; V
SS
= 0 V
Rev. 03 — 4 May 2009
Conditions
12-clock mode
6-clock mode
[1]
80C51 with 256 B RAM, 192 B data EEPROM
Min
0
0
2T
T
T
-
T
3T
-
0
-
T
-
-
6T
6T
-
0
-
-
-
3T
4T
T
7T
-
T
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
15
15
15
8
20
15
15
15
30
30
15
30
50
Max
40
20
-
-
-
4T
-
-
3T
-
T
-
5T
10
-
-
5T
-
2T
8T
9T
3T
-
-
-
0
T
P89V52X2
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
© NXP B.V. 2009. All rights reserved.
+ 15
+ 15
20
45
55
60
50
12
50
75
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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