LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 12

IC MCU 32BIT 32KB FLASH 48LQFP

LPC1313FBD48,151

Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheets

Specifications of LPC1313FBD48,151

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151

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NXP Semiconductors
3.5 Register description
UM10375
User manual
Fig 3.
wdt_osc_clk
sys_osc_clk
sys_osc_clk
irc_osc_clk
irc_osc_clk
USB is available in parts LPC134x only.
LPC13xx CGU block diagram
SYSPLLCLKSEL
USBPLLCLKSEL
sys_pllclkin
usb_pllclkin
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
See
the system setup. This register is not part of the system configuration block.
Section 3.11
MAINCLKSEL
sys_pllclkout
USB PLL
SYS PLL
All information provided in this document is subject to legal disclaimers.
for the flash access timing register, which can be re-configured as part
usb_pllclkout
main clock
Rev. 2 — 7 July 2010
wdt_osc_clk
wdt_osc_clk
sys_osc_clk
irc_osc_clk
irc_osc_clk
DIVIDER
CLOCK
CLKOUTUEN
WDTUEN
USBUEN
Chapter 3: LPC13xx System configuration
system clock
AHBCLKCTRL
(IOCON enable)
AHBCLKCTRL
(ROM enable)
DIVIDER
DIVIDER
DIVIDER
DIVIDER
CLOCK
CLOCK
CLOCK
CLOCK
DIVIDER
DIVIDER
DIVIDER
CLOCK
CLOCK
CLOCK
UM10375
sys_ahb_clk[0]
(system)
sys_ahb_clk[1]
(ROM)
sys_ahb_clk[16]
(IOCON)
© NXP B.V. 2010. All rights reserved.
SSP_PCLK
UART_PCLK
ARM trace clock
SYSTICK
timer
wdt_clk
usb_clk
clkout_clk
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