LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 178
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
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Quantity
Price
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LPC1313FBD48,151
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MAXIM
Quantity:
1 560
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Manufacturer:
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UM10375
User manual
11.6.12 UART Auto-baud Control Register (U0ACR - 0x4000 8020)
11.6.11 UART Scratch Pad Register (U0SCR - 0x4000 801C)
Table 199. UART Modem Status Register (U0MSR - address 0x4000 8018) bit description
The U0SCR has no effect on the UART operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the U0SCR has occurred.
Table 200. UART Scratch Pad Register (U0SCR - address 0x4000 8014) bit description
The UART Auto-baud Control Register (U0ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Bit Symbol Value Description
0
1
2
3
4
5
6
7
31:
8
Bit Symbol Description
7:0 Pad
31:
8
Delta
CTS
Delta
DSR
Trailing
Edge RI
Delta
DCD
CTS
DSR
RI
DCD
-
-
-
A readable, writable byte.
Reserved
All information provided in this document is subject to legal disclaimers.
0
1
0
1
0
1
0
1
Set upon state change of input CTS. Cleared on a U0MSR read.
No change detected on modem input CTS.
State change detected on modem input CTS.
Set upon state change of input DSR. Cleared on a U0MSR read.
No change detected on modem input DSR.
State change detected on modem input DSR.
Set upon low to high transition of input RI. Cleared on a U0MSR
read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Set upon state change of input DCD. Cleared on a U0MSR read.
No change detected on modem input DCD.
State change detected on modem input DCD.
Clear To Send State. Complement of input signal CTS. This bit is
connected to U0MCR[1] in modem loopback mode.
Data Set Ready State. Complement of input signal DSR. This bit is
connected to U0MCR[0] in modem loopback mode.
Ring Indicator State. Complement of input RI. This bit is connected
to U0MCR[2] in modem loopback mode.
Data Carrier Detect State. Complement of input DCD. This bit is
connected to U0MCR[3] in modem loopback mode.
Reserved
Rev. 2 — 7 July 2010
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
Reset Value
0x00
-
180 of 333
Reset
Value
0
0
0
0
0
0
0
0
-
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