LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 226
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
MAXIM
Quantity:
1 560
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
NXP Semiconductors
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NXP Semiconductors
UM10375
User manual
12.12.5.1 State: 0x00
12.12.5.2 Master States
12.12.5.3 State: 0x08
12.12.3 Start Master Receive function
12.12.4 I
12.12.5 Non mode specific states
Begin a Master Receive operation by setting up the buffer, pointer, and data count, then
initiating a START.
Determine the I
Bus Error. Enter not addressed Slave mode and release bus.
State 08 and State 10 are for both Master Transmit and Master Receive modes. The R/W
bit decides whether the next state is within Master Transmit mode or Master Receive
mode.
A START condition has been transmitted. The Slave Address + R/W bit will be
transmitted, an ACK bit will be received.
2
2. Set up the Slave Address to which data will be transmitted, and add the Write bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up data to be transmitted in Master Transmit buffer.
5. Initialize the Master data counter to match the length of the message being sent.
6. Exit
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the Read bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up the Master Receive buffer.
5. Initialize the Master data counter to match the length of the message to be received.
6. Exit
1. Read the I
2. Use the status value to branch to one of 26 possible state routines.
1. Write 0x14 to I2CONSET to set the STO and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit
1. Write Slave Address with R/W bit to I2DAT.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Set up Master Transmit mode data buffer.
C interrupt routine
2
2
C status from I2STA.
All information provided in this document is subject to legal disclaimers.
C state and which state routine will be used to handle it.
Rev. 2 — 7 July 2010
Chapter 12: LPC13xx I2C-bus controller
UM10375
© NXP B.V. 2010. All rights reserved.
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