LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 257
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
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UM10375
User manual
14.8.13 Rules for single edge controlled PWM outputs
Table 254. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
Note: When the match outputs are selected to serve as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0
except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to 1 to enable the timer reset when the timer value matches the value of the
corresponding match register.
Bit
0
1
2
3
31:4
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
3. If a match value larger than the PWM cycle length is written to the match register, and
4. If a match register contains the same value as the timer reset value (the PWM cycle
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
(timer is set to zero) unless their match value is equal to zero.
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
the PWM signal is HIGH already, then the PWM signal will be cleared on the next start
of the next PWM cycle.
length), then the PWM output will be reset to LOW on the next clock tick. Therefore,
the PWM output will always consist of a one clock tick wide positive pulse with a
period determined by the PWM cycle length (i.e. the timer reload value).
timer goes back to zero and will stay HIGH continuously.
Symbol
PWM enable
PWM enable
PWM enable
PWM enable
-
TMR16B1PWMC- address 0x4001 0074) bit description
All information provided in this document is subject to legal disclaimers.
Description
When one, PWM mode is enabled for CT16Bn_MAT0.
When zero, CT16Bn_MAT0 is controlled by EM0.
When one, PWM mode is enabled for CT16Bn_MAT1.
When zero, CT16Bn_MAT1 is controlled by EM1.
When one, PWM mode is enabled for match channel 2
or pin CT16B0_MAT2. When zero, match channel 2 or
pin CT16B0_MAT2 is controlled by EM2. Match channel
2 is not pinned out on timer 1.
When one, PWM mode is enabled for match channel
3match channel 3. When zero, match channel 3 is
controlled by EM3. Match channel 3 is not pinned out on
timer 1.
Note: It is recommended to use this channel match
channel 3 to set the PWM cycle because it is not pinned
out.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Rev. 2 — 7 July 2010
Chapter 14: LPC13xx 16-bit timer/counters (CT16B0/1)
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
0
0
NA
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