LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 43

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
3.8.3.1 Power configuration in Deep-sleep mode
3.8.3.2 Programming Deep-sleep mode
3.8.3 Deep-sleep mode
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG
register.
Deep-sleep mode eliminates all power used by the flash and analog peripherals and all
dynamic power used by the processor itself, memory systems and related controllers, and
internal buses. The processor state and registers, peripheral registers, and internal SRAM
values are maintained, and the logic levels of the pins remain static.
Power consumption in Deep-sleep mode is determined by the Deep-sleep power
configuration setting in the PDSLEEPCFG
The following steps must be performed to enter Deep-sleep mode:
1. The DPDEN bit in the PCON register must be set to zero
2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG
3. Select the power configuration after wake-up in the PDAWAKECFG
4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start
5. In the SYSAHBCLKCTRL register
6. Write one to the SLEEPDEEP bit in the ARM Cortex-M3 SCR register.
7. Use the ARM WFI instruction.
•
•
•
The only clock source available in Deep-sleep mode is the watchdog oscillator. The
watchdog oscillator can be left running in Deep-sleep mode if required for
timer-controlled wake-up (see
system oscillator) and the system PLL are shut down. The watchdog oscillator analog
output frequency must be set to the lowest value of its analog cock output (bits
FREQSEL in the WDTOSCCTRL = 0001, see
The BOD circuit can be left running in Deep-sleep mode if required by the application.
If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or
one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register
to minimize power consumption.
register.
a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is
b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down,
register.
logic registers
counter/timer or WDT if needed.
powered in the PDRUNCFG register and switch the clock source to WD oscillator
in the MAINCLKSEL register
ensure that the IRC is powered in the PDRUNCFG register and switch the clock
source to IRC in the MAINCLKSEL register
system clock is shut down glitch-free.
All information provided in this document is subject to legal disclaimers.
(Table 41
Rev. 2 — 7 July 2010
to
Table
Section
(Table
48), and enable the start logic interrupt in the NVIC.
(Table
3.9.3). All other clock sources (the IRC and
(Table
20).
Chapter 3: LPC13xx System configuration
23), disable all peripherals except
50) register:
Table
(Table
13).
20). This ensures that the
(Table
58).
UM10375
© NXP B.V. 2010. All rights reserved.
(Table
(Table
51)
44 of 333
50)