LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 233
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
MAXIM
Quantity:
1 560
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
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13.1 How to read this chapter
13.2 Basic configuration
13.3 Features
13.4 General description
UM10375
User manual
The SSP block is identical for all LPC13xx parts.
The SSP is configured using the following registers:
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
The LPC13xx has one Synchronous Serial Port controller.
1. Pins: The SSP pins must be configured in the IOCONFIG register block
2. Power: In the SYSAHBCLKCTRL register, set bit 11
3. Peripheral clock: Enable the SSP peripheral clock by writing to the SSP0CLKDIV
4. Reset: Before accessing the SSP block, ensure that the SSP_RST_N bit (bit 0) in the
•
•
•
•
•
UM10375
Chapter 13: LPC13xx SSP
Rev. 2 — 7 July 2010
(Section
register
PRESETCTRL register
SSP block.
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
Synchronous Serial Communication.
Supports master or slave operation.
Eight frame FIFOs for both transmit and receive.
4-bit to 16-bit frame.
(Table
6.4.1).
All information provided in this document is subject to legal disclaimers.
24).
Rev. 2 — 7 July 2010
(Table
7) is set to 1. This de-asserts the reset signal to the
(Table
23).
© NXP B.V. 2010. All rights reserved.
User manual
235 of 333
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