LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 4

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
5. Block diagram
LPC2470
Product data sheet
Fig 1.
6 × PWM0/PWM1
2 × CAP0/CAP1/
4 × MAT2/MAT3,
EINT3 to EINT0
power domain 2
CAP2/CAP3
1 × PCAP0,
2 × PCAP1
P0, P1, P2,
2 × MAT0,
3 × MAT1
MII/RMII
8 × AD0
ALARM
LPC2470 block diagram
RTCX1
RTCX2
P0, P2
P0, P1
AOUT
P3, P4
VBAT
HIGH-SPEED
ETHERNET
LPC2470
MAC WITH
OSCILLATOR
160 PINS
DMA
GPIO
TOTAL
EXTERNAL INTERRUPTS
RTC
CAPTURE/COMPARE
2 kB BATTERY RAM
SYSTEM CONTROL
WATCHDOG TIMER
A/D CONVERTER
D/A CONVERTER
TIMER0/TIMER1/
TIMER2/TIMER3
LEGACY GPI/O
64 PINS TOTAL
PWM0, PWM1
AHB2
SRAM
16 kB
CONTROLLER
INTERNAL
SRAM
SRAM
64 kB
CLOCK
REAL-
TIME
All information provided in this document is subject to legal disclaimers.
BRIDGE
MASTER
PORT
TRST
AHB
Rev. 3 — 14 February 2011
ARM7TDMI-S
TMS
TEST/DEBUG
INTERFACE
TCK TDO
AHB BRIDGE
APB BRIDGE
AHB TO
TDI
AHB TO
EXTIN0
trace signals
BRIDGE
AHB
SLAVE
PORT
DBGEN
VIC
system
clock
PLL
SPI, SSP0 INTERFACE
UART0, UART2, UART3
Flashless 16-bit/32-bit microcontroller
SRAM
SSP1 INTERFACE
16 kB
I
SD/MMC CARD
I
RESET
4 kB RAM AND DMA
2
2
HOST/OTG WITH
CAN1, CAN2
S INTERFACE
INTERFACE
C0, I
LCD INTERFACE
USB DEVICE/
CONTROLLER
UART1
INTERNAL RC
XTAL2
OSCILLATOR
AHB1
FUNCTIONS
WITH DMA
2
C1, I
GP DMA
CONTROLLER
SYSTEM
EXTERNAL
XTAL1
MEMORY
2
C2
V
DDA
002aad317
V
DD(3V3)
LPC2470
VREF
V
V
© NXP B.V. 2011. All rights reserved.
A[23:0]
control lines
V
port1
port2
8 × LCD control
LCDVD[23:0]
LCDCLKIN
3 × I2SRX
3 × I2STX
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1, DTR1, RTS1
RXD1, DSR1, CTS1,
DCD1, RI1
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
D[31:0]
SSA
DD(DCDC)(3V3)
BUS
, V
SSCORE
, V
4 of 89
SSIO