P80C554SFBD,157 NXP Semiconductors, P80C554SFBD,157 Datasheet - Page 19

• Manufacturer Part Number: P80C554SFBD,157
• Description: IC 80C51 MCU 8BIT ROMLESS 64LQFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C554SFBD,157

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 8 MHz, 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-2086; 935268881157; P80C554SFBD

Philips Semiconductors
When a match with CM1 occurs, the controller resets bits 0-5 of port
4 if the corresponding bits of the reset/toggle enable register RTE
are at logic 1 (see Figure 15 for RTE register function). If RTE is “0”,
then P4.n is not affected by a match between CM1 or CM2 and
Timer 2. When a match with CM2 occurs, the controller “toggles”
bits 6 and 7 of port 4 if the corresponding bits of the RTE are at
logic 1. The port latches of bits 6 and 7 are not toggled.
Two additional flip-flops store the last operation, and it is these
flip-flops that are toggled.
Thus, if the current operation is “set,” the next operation will be
“reset” even if the port latch is reset by software before the “reset”
operation occurs. The first “toggle” after a chip RESET will set the
port latch. The contents of these two flip-flops can be read at STE.6
and STE.7 (corresponding to P4.6 and P4.7, respectively). Bits
STE.6 and STE.7 are read only (see Figure 16 for STE register
function). A logic 1 indicates that the next toggle will set the port
latch; a logic 0 indicates that the next toggle will reset the port latch.
CM0, CM1, and CM2 are reset by the RST signal.
The modified port latch information appears at the port pin during
S5P1 of the cycle following the cycle in which a match occurred. If
the port is modified by software, the outputs change during S1P1 of
the following cycle. Each port 4 bit can be set or reset by software at
any time. A hardware modification resulting from a comparator
match takes precedence over a software modification in the same
cycle. When the comparator results require a “set” and a “reset” at
the same time, the port latch will be reset.
2003 Jan 28
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
CTCON (EBH)
RTE (EFH)
BIT
CTCON.7
CTCON.6
CTCON.5
CTCON.4
CTCON.3
CTCON.2
CTCON.1
CTCON.0
BIT
RTE.7
RTE.6
RTE.5
RTE.4
RTE.3
RTE.2
RTE.1
RTE.0
(MSB)
(MSB)
CTN3
TP47
7
7
CTP3
TP46
SYMBOL
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
SYMBOL
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
6
6
Figure 15. Reset/Toggle Enable Register (RTE)
Figure 14. Capture Control Register (CTCON)
CTN2
RP45
5
5
CAPTURE/INTERRUPT ON:
Capture Register 3 triggered by a falling edge on CT3I
Capture Register 3 triggered by a rising edge on CT3I
Capture Register 2 triggered by a falling edge on CT2I
Capture Register 2 triggered by a rising edge on CT2I
Capture Register 1 triggered by a falling edge on CT1I
Capture Register 1 triggered by a rising edge on CT1I
Capture Register 0 triggered by a falling edge on CT0I
Capture Register 0 triggered by a rising edge on CT0I
FUNCTION
If “1” then P4.7 toggles on a match between CM1 and Timer T2
If “1” then P4.6 toggles on a match between CM1 and Timer T2
If “1” then P4.5 is reset on a match between CM1 and Timer T2
If “1” then P4.4 is reset on a match between CM1 and Timer T2
If “1” then P4.3 is reset on a match between CM1 and Timer T2
If “1” then P4.2 is reset on a match between CM1 and Timer T2
If “1” then P4.1 is reset on a match between CM1 and Timer T2
If “1” then P4.0 is reset on a match between CM1 and Timer T2
CTP2
RP44
4
4
2
C, PWM, capture/compare,
19
CTN1
RP43
3
3
Timer T2 Interrupt Flag Register TM2IR: Eight of the nine Timer
T2 interrupt flags are located in special function register TM2IR (see
Figure 17). The ninth flag is TM2CON.4.
The CT0I and CT1I flags are set during S4 of the cycle in which the
contents of Timer T2 are captured. CT0I is scanned by the interrupt
logic during S2, and CT1I is scanned during S3. CT2I and CT3I are
set during S6 and are scanned during S4 and S5. The associated
interrupt requests are recognized during the following cycle. If these
flags are polled, a transition at CT0I or CT1I will be recognized one
cycle before a transition on CT2I or CT3I since registers are read
during S5. The CMI0, CMI1, and CMI2 flags are set during S6 of the
cycle following a match. CMI0 is scanned by the interrupt logic
during S2; CMI1 and CMI2 are scanned during S3 and S4. A match
will be recognized by the interrupt logic (or by polling the flags) two
cycles after the match takes place.
The 16-bit overflow flag (T2OV) and the byte overflow flag (T2BO)
are set during S6 of the cycle in which the overflow occurs. These
flags are recognized by the interrupt logic during the next cycle.
Special function register IP1 (Figure 17) is used to determine the
Timer T2 interrupt priority. Setting a bit high gives that function a
high priority, and setting a bit low gives the function a low priority.
The functions controlled by the various bits of the IP1 register are
shown in Figure 17.
CTP1
RP42
2
2
CTN1
RO41
1
1
CTP0
(LSB)
(LSB)
RP40
0
0
80C554/87C554
Reset Value = 00H
Reset Value = 00H
Product data
SU01086
SU01085