P80C554SFBD,157 NXP Semiconductors, P80C554SFBD,157 Datasheet - Page 26

• Manufacturer Part Number: P80C554SFBD,157
• Description: IC 80C51 MCU 8BIT ROMLESS 64LQFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C554SFBD,157

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 8 MHz, 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-2086; 935268881157; P80C554SFBD

Philips Semiconductors
2003 Jan 28
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
ADCON.7
ADCON.6
ADCON.5
ADCON.4
ADCON.3
ADCON.2
ADCON.1
ADCON.0
Bit
Symbol
ADC.1
ADC.0
ADEX
ADCI
ADCS
AADR2
AADR1
AADR0
ADCON (C5H)
Bit 1 of ADC result
Bit 0 of ADC result
Enable external start of conversion by STADC
0 = Conversion can be started by software only (by setting ADCS)
1 = Conversion can be started by software or externally (by a rising edge on STADC)
ADC interrupt flag: this flag is set when an A/D conversion result is ready to be read. An interrupt is
invoked if it is enabled. The flag may be cleared by the interrupt service routine. While this flag is set,
the ADC cannot start a new conversion. ADCI cannot be set by software.
ADC start and status: setting this bit starts an A/D conversion. It may be set by software or by the
external signal STADC. The ADC logic ensures that this signal is HIGH while the ADC is busy. On
completion of the conversion, ADCS is reset immediately after the interrupt flag has been set. ADCS
cannot be reset by software. A new conversion may not be started while either ADCS or ADCI is high.
Analogue input select: this binary coded address selects one of the
eight analogue port bits of P5 to be input to the converter. It can only
be changed when ADCI and ADCS are both LOW.
If ADCI is cleared by software while ADCS is set at the same time, a new A/D conversion with the
same channel number may be started.
But it is recommended to reset ADCI before ADCS is set.
Function
(MSB)
AADR2
ADC.1
7
ADCI
0
0
0
0
1
1
1
0
0
1
1
ADC.0
AADR1
6
Figure 23. ADC Control Register (ADCON)
0
0
1
1
0
0
1
ADCS
0
1
0
1
ADEX
5
AADR0
0
1
0
1
0
1
0
ADC not busy; a conversion can be started
ADC busy; start of a new conversion is blocked
Conversion completed; start of a new conversion requires ADCI=0
Conversion completed; start of a new conversion requires ADCI=0
ADCI ADCS
4
2
C, PWM, capture/compare,
26
3
Selected Analog Channel
ADC Status
AADR2 AADR1
2
ADC0 (P5.0)
ADC1 (P5.1)
ADC2 (P5.2)
ADC3 (P5.3)
ADC4 (P5.4)
ADC5 (P5.5)
ADC6 (P5.6)
1
AADR0
0
(LSB)
Reset Value = xx00 0000B
80C554/87C554
SU01468
Product data