P80C554SFBD,157 NXP Semiconductors, P80C554SFBD,157 Datasheet - Page 54

• Manufacturer Part Number: P80C554SFBD,157
• Description: IC 80C51 MCU 8BIT ROMLESS 64LQFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C554SFBD,157

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 8 MHz, 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-2086; 935268881157; P80C554SFBD

Philips Semiconductors
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2003 Jan 28
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
4100
75DB31
D296
D297
755001
43A8A0
C2BD
75D8C5
755204
7551C0
D2DD
755204
7551C1
D2DD
C0D0
C0D9
C050
22
75D8D5
D0D0
32
!********************************************************************************************************
! INITIALIZATION ROUTINE
! Example to initialize IIC Interface as slave receiver or slave transmitter and
! start a MASTER TRANSMIT or a MASTER RECEIVE function. 4 bytes will be transmitted or received.
!********************************************************************************************************
.sect
.base
.sect
.base
INIT:
!********************************************************************************************************
!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
! START MASTER TRANSMIT FUNCTION
!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
! START MASTER RECEIVE FUNCTION
!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
!********************************************************************************************************
! SI01 INTERRUPT ROUTINE
!********************************************************************************************************
.sect
.base
! S1STA and HADD are pushed onto the stack.
! They serve as return address for the RET instruction.
! The RET instruction sets the Program Counter to address HADD,
! S1STA and jumps to the right subroutine.
!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
! STATE
! ACTION : Enter not addressed SLV mode and release bus. STO reset.
!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
.sect
.base
strt
0x00
initial
0x200
intvec
0x00
: 00, Bus error.
st0
0x100
ajmp INIT
mov
setb
setb
mov
orl
clr
mov
mov
mov
setb
mov
mov
setb
push psw
push S1STA
push HADD
ret
mov
pop
reti
2
S1ADR,#OWNSLA
P1(6)
P1(7)
HADD,#PAG1
IEN0,#ENSI01
SI01HP
S1CON, #ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0
NUMBYTMST,#0x4
SLA,#SLAW
STA
NUMBYTMST,#0x4
SLA,#SLAR
STA
S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! clr SI
psw
C, PWM, capture/compare,
54
! RESET
! Load own SLA + enable
! general call recognition
! P1.6 High level.
! P1.7 High level.
! Enable SI01 interrupt
! SI01 interrupt low priority
! Initialize SLV funct.
! Transmit 4 bytes.
! SLA+W, Transmit funct.
! set STA in S1CON
! Receive 4 bytes.
! SLA+R, Receive funct.
! set STA in S1CON
! SI01 interrupt vector
! save psw
! JMP to address HADD,S1STA.
! set STO,AA
80C554/87C554
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