P80C554SFBD,157 NXP Semiconductors, P80C554SFBD,157 Datasheet - Page 2

• Manufacturer Part Number: P80C554SFBD,157
• Description: IC 80C51 MCU 8BIT ROMLESS 64LQFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C554SFBD,157

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 8 MHz, 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-2086; 935268881157; P80C554SFBD

reduction—idle mode and power-down mode. The idle mode freezes
Philips Semiconductors
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
capture/compare, high I/O, 64L LQFP
8DESCRIPTION
This data sheet describes the 6 clock version of the 8xC554. This
device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit
Microcontroller is manufactured in an advanced CMOS process and
is a derivative of the 80C51 microcontroller family. The 87C554 has
the same instruction set as the 80C51. Three versions of the
derivative exist:
The 87C554 contains a 16k
read/write data memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, four-priority-level, nested interrupt structure, an 7-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I
oscillator and timing circuits. For systems that require extra
capability, the 8xC554 can be expanded using standard TTL
compatible memories and logic.
In addition, the 8xC554 has two software selectable modes of power
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. Optionally, the ADC can be operated
in Idle mode. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions:
49 one-byte, 45 two-byte, and 17 three-byte. With an 8-MHz crystal,
58% of the instructions are executed in 0.75 s and 40% in 1.5 s.
Multiply and divide instructions require 3 s.
2003 Jan 28
80C554—ROMless version
87C554—16 kbytes EPROM
2
C-bus), a “watchdog” timer and on-chip
8 non-volatile EPROM, a 512
8
2
C, PWM,
2
FEATURES
80C51 central processing unit
16k
An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
Two standard 16-bit timer/counters
512
Capable of producing eight synchronized, timed outputs
A 10-bit ADC with seven multiplexed analog inputs
Fast 8-bit ADC option – 9 S at 16 MHz
Two 8-bit resolution, pulse width modulation outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
I
functions
On-chip watchdog timer
Extended temperature ranges
Full static operation – 0 to 16 MHz
Operating voltage range: 2.7 V to 5.5 V (0 to 8 MHz) and
4.5 V to 5.5 V (8 to 16 MHz) commercial temperature
Security bits:
– ROM – 2 bits
– OTP/EPROM – 3 bits
Four interrupt priority levels
15 interrupt sources
Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
Power control modes
– Clock can be stopped and resumed
– Idle mode
– Power down mode
Second DPTR register
EMI reduction – 6 clock operation and ALE inhibit
Programmable I/O pins
Wake-up from power-down by external interrupts
Software reset
Power-on detect reset
ADC charge pump disable
ONCE mode
ADC active in Idle mode
2
C-bus serial I/O port with byte oriented master and slave
8 EPROM expandable externally to 64 kbytes
8 RAM, expandable externally to 64 kbytes
80C554/87C554
853-2408 29338
Product data