ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 109

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
Note:
SPI Data I/O Register (SPIDR)
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see
Table 58.
SPIDR
Address (Hex.) Register label
R/W
D7
0021h
0022h
0023h
7
Warning:
SPI register map and reset values
R/W
D6
SPIDR
Reset value
SPICR
Reset value
SPICSR
Reset value
6
A write to the SPIDR register places data directly into the
shift register for transmission.
Figure
R/W
D5
5
48).
Doc ID13466 Rev 4
SPIE
MSB
SPIF
7
x
0
0
R/W
D4
4
WCOL
SPE
6
x
0
0
SPR2
OVR
R/W
5
x
0
0
D3
3
MODF
MSTR
4
0
0
x
R/W
D2
2
CPOL
3
x
x
0
Reset value: undefined
On-chip peripherals
CPHA
SOD
R/W
2
0
x
x
D1
1
SPR1
SSM
1
x
x
0
R/W
109/198
D0
0
SPR0
LSB
SSI
0
0
x
x