ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 31

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
6
6.1
6.2
Caution:
Supply, reset and clock management
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in
For more details, refer to dedicated parametric section.
Main features
●
●
●
●
PLL (phase locked loop)
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f
byte. If the PLL is disabled, then f
The PLL is not recommended for applications where timing accuracy is required.
Furthermore, it must not be used with the internal RC oscillator.
Figure 9.
Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used
with internal RC oscillator in order to respect the max. operating frequency)
Multi-Oscillator clock management (MO)
–
–
Reset Sequence Manager (RSM)
System Integrity management (SI)
–
–
5 crystal/ceramic resonator oscillators
1 Internal RC oscillator
Main supply low voltage detection (LVD)
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
PLL block diagram
f
OSC
Doc ID13466 Rev 4
OSC2
PLL x 2
Figure
= f
/ 2
OSC
OSC2
10.
/2.
of 4 to 8 MHz. The PLL is enabled by option
PLL option bit
Supply, reset and clock management
0
1
f
OSC2
31/198