ST72F324BJ6T6 STMicroelectronics, ST72F324BJ6T6 Datasheet - Page 133

• Manufacturer Part Number: ST72F324BJ6T6
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5590

ST72324B-Auto
10.6.4
Note:
10.6.5
10.6.6
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Table 70.
Interrupts
None.
ADC registers
ADC Control/Status Register (ADCCSR)
Table 71.
ADCCSR
Bit
.
7
6
EOC
Mode
RO
Wait
Halt
7
SPEED
Name
EOC
Effect of low power modes on ADC
ADCCSR register description
SPEED
No effect on A/D converter
A/D converter disabled.
After wake-up from Halt mode, the A/D converter requires a stabilization time t
(see
performed.
End of Conversion
ADC clock selection
R/W
This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
This bit is set and cleared by software.
0: f
1: f
6
Section 12: Electrical
ADC
ADC
= f
= f
ADON
CPU
CPU
RW
5
/4
/2
Doc ID13466 Rev 4
Reserved
characteristics) before accurate conversions can be
4
-
Description
Function
3
2
Reset value: 0000 0000 (00h)
CH[3:0]
RW
On-chip peripherals
1
STAB
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