C8051T606-ZM Silicon Laboratories Inc, C8051T606-ZM Datasheet - Page 120
![IC 8051 MCU 1.5K-EEPROM 10-QFN](/photos/12/15/121567/10-qfn_pkg_sml.jpg)
C8051T606-ZM
Manufacturer Part Number
C8051T606-ZM
Description
IC 8051 MCU 1.5K-EEPROM 10-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Specifications of C8051T606-ZM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
10-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T606DK
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Data Converters
-
For Use With
336-1668 - CARD DAUGHTER QFN10 SOCKET336-1667 - CARD DAUGHTER MSOP SOCKET336-1666 - KIT DEVELOPMENT FOR C8051T606336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1663-2
C8051T606-ZMR
C8051T606-ZMR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T606-ZMR
Manufacturer:
STM
Quantity:
4 037
C8051T600/1/2/3/4/5/6
23. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. A block diagram of the SMBus peripheral and
the associated SFRs is shown in Figure 23.1.
120
M
A
S
T
E
R
Interrupt
Request
M
O
T
X
D
E
SMB0CN
S
T
A
S
O
T
Q
A
C
K
R
R
O
A
B
L
S
T
A
C
K
S
I
IRQ Generation
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
SMBUS CONTROL LOGIC
Figure 23.1. SMBus Block Diagram
M
E
N
S
B
N
H
I
SMB0CF
B
U
S
Y
O
E
X
T
H
D
L
M
O
S
B
T
E
M
S
B
E
F
T
M
S
B
C
S
1
7
M
C
S
B
S
0
6
Data Path
SMB0DAT
5
Control
4
3
Rev. 1.2
2
1
0
00
01
10
11
Control
SDA
Control
SCL
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
2
N
N
C serial bus. Reads and writes to
SDA
SCL
C
R
O
R
S
S
B
A
Port I/O