C8051T606-ZM Silicon Laboratories Inc, C8051T606-ZM Datasheet - Page 73
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C8051T606-ZM
Manufacturer Part Number
C8051T606-ZM
Description
IC 8051 MCU 1.5K-EEPROM 10-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Specifications of C8051T606-ZM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
10-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T606DK
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Data Converters
-
For Use With
336-1668 - CARD DAUGHTER QFN10 SOCKET336-1667 - CARD DAUGHTER MSOP SOCKET336-1666 - KIT DEVELOPMENT FOR C8051T606336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1663-2
C8051T606-ZMR
C8051T606-ZMR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T606-ZMR
Manufacturer:
STM
Quantity:
4 037
SFR Definition 14.6. PSW: Program Status Word
SFR Address = 0xD0; Bit-Addressable
Name
Reset
Bit
4:3
Type
7
6
5
2
1
0
Bit
PARITY
RS[1:0]
Name
CY
AC
OV
F0
F1
R/W
CY
7
0
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
Overflow Flag.
This bit is set to 1 under the following circumstances:
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
R/W
AC
6
0
R/W
F0
5
0
Rev. 1.2
4
0
RS[1:0]
R/W
Function
C8051T600/1/2/3/4/5/6
3
0
R/W
OV
2
0
R/W
F1
1
0
PARITY
R
0
0
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