C8051T606-ZM Silicon Laboratories Inc, C8051T606-ZM Datasheet - Page 132
![IC 8051 MCU 1.5K-EEPROM 10-QFN](/photos/12/15/121567/10-qfn_pkg_sml.jpg)
C8051T606-ZM
Manufacturer Part Number
C8051T606-ZM
Description
IC 8051 MCU 1.5K-EEPROM 10-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Specifications of C8051T606-ZM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
10-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T606DK
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Data Converters
-
For Use With
336-1668 - CARD DAUGHTER QFN10 SOCKET336-1667 - CARD DAUGHTER MSOP SOCKET336-1666 - KIT DEVELOPMENT FOR C8051T606336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1663-2
C8051T606-ZMR
C8051T606-ZMR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T606-ZMR
Manufacturer:
STM
Quantity:
4 037
C8051T600/1/2/3/4/5/6
23.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
The ACKRQ bit is set to 1 and an interrupt is generated after each received byte. Software must write the
ACK bit at that time to ACK or NACK the received byte.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if
SMB0DAT is written while an active Master Receiver. Figure 23.6 shows a typical master read sequence.
Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data
byte transferred’ interrupts occur before the ACK.
132
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 23.6. Typical Master Read Sequence
R
A
Interrupt Locations
Data Byte
Rev. 1.2
A
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
N
P