R5F21237DFP#U0 Renesas Electronics America, R5F21237DFP#U0 Datasheet - Page 209
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/18/121887/r5f21237dfp_u0_sml.jpg)
R5F21237DFP#U0
Manufacturer Part Number
R5F21237DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21237DFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.39
Timer RD I/O Control Register Ai (i = 0 or 1)
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
1
When selecting 1 (The TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi
bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
When selecting 1 (The TRDGRDi register is used as a buffer register of TRDGRBi register) for this bit by the BFDi bit
in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
The IOA3 bit in the only TRDIORA0 register is enabled. Set to the IOA3 bit in the TRDIORA1 to 1.
The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
b3 b2
1
Registers TRDIORA0 to TRDIORA1 in Input Capture Function
b1 b0
TRDIORA0
TRDIORA1
Bit Symbol
Symbol
Page 187 of 501
IOA0
IOA1
IOA2
IOA3
IOB0
IOB1
IOB2
(b7)
—
TRDGRA control bit
TRDGRA mode selection bit
Input capture input sw itch
bit
TRDGRB control bit
TRDGRB mode selection bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
(3,4)
Address
Bit Name
0141h
0151h
(2)
(1)
b1 b0
0 0 : Input capture to the TRDGRAi register
0 1 : Input capture to the TRDGRAi register
1 0 : Input capture to the TRDGRAi register
1 1 : Do not set
b5 b4
0 0 : Input capture to the TRDGRBi register
0 1 : Input capture to the TRDGRBi register
1 0 : Input capture to the TRDGRBi register
1 1 : Do not set
Set to 1 (input capture) in the input capture
function
0 : fOCO128 Signal
1 : TRDIOA0 pin
Set to 1 (input capture) in the input capture
function
at the rising edge
at the falling edge
at both edges
at the rising edge
at the falling edge
at both edges
After Reset
10001000b
10001000b
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
—
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