R5F21237DFP#U0 Renesas Electronics America, R5F21237DFP#U0 Datasheet - Page 299
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/18/121887/r5f21237dfp_u0_sml.jpg)
R5F21237DFP#U0
Manufacturer Part Number
R5F21237DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21237DFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 15.3
UARTi Bit Rate Register (i = 0 or 1)
UARTi Receive Buffer Register (i = 0 or 1)
UARTi Transmit Buffer Register (i = 0 or 1)
(b15)
(b15)
b7
NOTES:
b7
NOTES:
b7
NOTES:
1.
2.
3.
1.
2.
1.
2.
Write to this register w hile the serial interface is neither transmitting nor receiving.
Use the MOV instruction to w rite to this register.
After setting the CLK0 to CLK1 bits in the UiC0 register, w rite to the UiBRG register.
Read out the UiRB register in 16-bit unit.
The SUM, PER, FER and OER bits are set to 0 (no error) w hen the SMD2 to SMD0 bits in the UiMR register are set to
000b (serial interface disabled) or the RE bit in the U0C1 register is set to 0 (receive disable). The SUM bit is set to 0
(no error) w hen the PER, FER and OER bits are set to 0 (no error). Also, the PER and FER bits are set to 0 w hen the
higher byte of the UiRB register is read out.
When the transfer data length is 9-bit long, w rite to high-byte data first then low -byte data.
Use the MOV instruction to w rite to this register.
Registers UiTB, UiRB, and UiBRG (i = 0 or 1)
(b8)
(b8)
b0
b0
b0
b7
b7
Assuming that set value is n, UiBRG divides the count source by
n+1
Bit Symbol
Bit Symbol
(b11-b9)
Symbol
U0BRG
U1BRG
(b15-b9)
(b7-b0)
(b8-b0)
SUM
Page 277 of 501
(b8)
OER
FER
PER
—
—
—
—
—
Nothing is assigned. If necessary, set to 0.
When read, the content is indeterminate.
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Transmit data
Nothing is assigned. If necessary, set to 0.
When read, the content is indeterminate.
b0
b0
(1,2,3)
Symbol
U0RB
U1RB
Symbol
U0TB
U1TB
(1)
(1,2)
(2)
Bit Name
Function
(2)
—
—
(2)
(2)
Address
00A1h
00A9h
00A7h-00A6h
00AFh-00AEh
00ABh-00AAh
00A3h-00A2h
Address
Address
Function
Receive data (D7 to D0)
Receive data (D8)
0 : No overrun error
1 : Overrun error
0 : No framing error
1 : Framing error
0 : No parity error
1 : Parity error
0 : No error
1 : Error
Function
Setting Range
Indeterminate
Indeterminate
After Reset
00h to FFh
Indeterminate
Indeterminate
Indeterminate
Indeterminate
After Reset
After Reset
15. Serial Interface
WO
RW
WO
RW
—
RW
RO
RO
RO
RO
RO
RO
—
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