R5F21237DFP#U0 Renesas Electronics America, R5F21237DFP#U0 Datasheet - Page 340
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/18/121887/r5f21237dfp_u0_sml.jpg)
R5F21237DFP#U0
Manufacturer Part Number
R5F21237DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21237DFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.2.6.3
Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode). During the data receive, the clock synchronous serial I/O with
chip select operates as described below.
When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock
and inputs data. When the clock synchronous serial I/O with chip select is set as a salve device, it outputs data
synchronized with the input clock while the SCS pin is held “L” input. When the clock synchronous serial I/O
with chip select is set as a master device, it outputs a receive clock and starts receiving by performing dummy
read on the SSRDR register.
After the 8-bit data is received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (enables RXI and
OEI interrupt request), the RXI interrupt request is generated. If the SSRDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). The clock synchronous serial I/O with chip select outputs a clock for receiving
8-bit data and stops. After that, set the RE bit in the SSER register to 0 (disables receive) and the RSSTP bit to
0 (receive operation is continued after receiving 1-byte data) and read the receive data. If the SSRDR register is
read while the RE bit is set to 1 (enables receive), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error occurs: OEI) and the operation is stopped. When the ORER bit is set to 1, receive can not be performed.
Confirm that the ORER bit is set to 0 before restarting receive.
When the RDRF and ORER bits are set to 1, it varies depending on setting the CPHS bit in the SSMR register.
Figure 16.20 shows when the RDRF and ORER bits are set to 1.
When the CPHS bit is set to 1 (data download at the odd edges), the RDRF and ORER bits are set to 1 at one
point of a frame.
A sample flowchart is the same as the clock synchronous communication mode (refer to Figure 16.16 Sample
Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
Data Reception
Page 318 of 501
16. Clock Synchronous Serial Interface
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