R5F21237DFP#U0 Renesas Electronics America, R5F21237DFP#U0 Datasheet - Page 311

• Manufacturer Part Number: R5F21237DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21237DFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 15.11
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
UiBRG output
UiC1 register
RE bit
RXDi
Transfer clock
UiC1 register
RI bit
SiRIC register
RI bit
The above timing diagram applies to the case where the register bits are set as follows:
i = 0 or 1
Receive Timing Example in UART Mode
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
1
0
1
0
1
0
Reception triggered when transfer clock
is generated by falling edge of start bit
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Start bit
Determined “L”
D0
Receive data taken in
Set to
0
when interrupt request is accepted, or set by a program
D1
Transferred from UARTi receive
register to UiRB register
D7
Stop bit
15. Serial Interface