R5F21237DFP#U0 Renesas Electronics America, R5F21237DFP#U0 Datasheet - Page 459
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/18/121887/r5f21237dfp_u0_sml.jpg)
R5F21237DFP#U0
Manufacturer Part Number
R5F21237DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21237DFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
20.4.5
Table 20.6
NOTE:
FMR07(SR5) FMR06(SR4)
1. The MCU enters read array mode by writing FFh in the second bus cycle of these commands, at the
FMR0 Register (Status
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to 1, indicating occurrence of
each specific error. Therefore, checking these status bits (full status check) can determine the executed result.
Table 20.6 lists the Errors and FMR0 Register Status. Figure 20.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
same time the command code written in the first bus cycle will disabled.
1
1
0
Register) Status
Full Status Check
Errors and FMR0 Register Status
1
0
1
Page 437 of 501
Command
sequence
error
Erase error
Program error
Error
• When the program command is executed but not
• When any command is not written correctly
• When invalid data other than those that can be written
• When executing the program command or block erase
• When inputting and erasing the address in which the
• When executing to erase the block which disables
• When inputting and writing the address in which the
• When executing to write the block which disables
• When the block erase command is executed but not
in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh)
command while rewriting is disabled using the FMR02
bit in the FMR0 register, the FMR15 or FMR16 bit in the
FMR1 register.
Flash memory is not allocated during the erase
command input
rewriting during the erase command input.
Flash memory is not allocated during the write
command input.
rewriting during the write command input.
automatically erased correctly
automatically programmed correctly.
Error Occurrence Condition
(1)
20. Flash Memory
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