R5F21237DFP#U0 Renesas Electronics America, R5F21237DFP#U0 Datasheet - Page 508
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/18/121887/r5f21237dfp_u0_sml.jpg)
R5F21237DFP#U0
Manufacturer Part Number
R5F21237DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21237DFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
22.7
22.7.1
Table 22.2
3 fCAN Period = 3 x XIN (Original Oscillation Period) x Division Value of CAN Clock (CCLK)
(Example 1) Condition XIN 16 MHz CCLK: Divided by 1 3 fCAN period = 3 x 62.5 ns x 1 = 187.5 ns
(Example 2) Condition XIN 16 MHz CCLK: Divided by 2 3 fCAN period = 3 x 62.5 ns x 2 = 375 ns
(Example 3) Condition XIN 16 MHz CCLK: Divided by 4 3 fCAN period = 3 x 62.5 ns x 4 = 750 ns
(Example 4) Condition XIN 16 MHz CCLK: Divided by 8 3 fCAN period = 3 x 62.5 ns x 8 = 1.5 µs
(Example 5) Condition XIN 16 MHz CCLK: Divided by 16 3 fCAN period = 3 x 62.5 ns x 16 = 3 µs
The CAN module updates the status of the C0STR register in a certain period. When the CPU and the CAN
module access to the C0STR register at the same time, the CPU has the access priority; the access from the
CAN module is disabled. Consequently, when the updating period of the CAN module matches the access
period from the CPU, the status of the CAN module cannot be updated. (See Figure 22.8)
Accordingly, be careful about the following points so that the access period from the CPU should not match the
updating period of the CAN module:
Notes on CAN Module
•
•
There should be a wait time of 3fCAN or longer (see Table 22.2) before the CPU reads the C0STR register.
(See Figure 22.9)
When the CPU polls the C0STR register, the polling period must be 3fCAN or longer. (See Figure 22.10)
Reading C0STR Register
CAN Module Status Updating Period
Page 486 of 501
22. Usage Notes
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