MC56F8346MFVE Freescale Semiconductor, MC56F8346MFVE Datasheet - Page 120

• Manufacturer Part Number: MC56F8346MFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346MFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 62
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.8.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
This bit selects the alternate function for GPIOC3.
120
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
GPIO Input
GPIO Output
Quad Timer Input / Quad
Decoder Input
Quad Timer Output / Quad
Decoder Input
SPI input
SPI output
used for each pin.
•
•
Base + $B
Pin Function
RESET
Read
Write
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User Manual)
1 = SS1
Reserved—Bits 15–4
GPIOC3 (C3)—Bit 3
2
3
15
0
0
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
14
Table 6-2 Control of Pads Using SIM_GPS Control
0
0
13
0
0
1
1
1
1
0
0
12
0
0
—
—
—
—
0
1
Control Registers
11
0
0
56F8346 Technical Data, Rev. 15
10
0
0
9
0
0
—
—
0
0
1
1
8
0
0
7
0
0
—
—
—
—
0
1
6
0
0
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of the timer inputs based on
the Quad Decoder Mode configuration.
See SPI controls for determining the direction
of each of the SPI pins.
5
0
0
4
0
0
C3
3
0
Comments
1
Freescale Semiconductor
C2
2
0
C1
1
0
Preliminary
C0
0
0