MC56F8346MFVE Freescale Semiconductor, MC56F8346MFVE Datasheet - Page 150

• Manufacturer Part Number: MC56F8346MFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346MFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 62
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
150
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
RESET Assertion to Address, Data and Control Signals
High Impedance
Minimum RESET Assertion Duration
RESET Deassertion to First External Address Output
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
Delay from IRQA Assertion (exiting Wait) to External Data
Memory access
Delay from IRQA Assertion to External Data Memory
Access (exiting Stop)
IRQA Width Assertion to Recover from Stop State
modes), T = 125ns.
not the minimum required so that the IRQA interrupt is accepted.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
4
Characteristic
56F8346 Technical Data, Rev. 15
5
3
t
IDM - FAST
t
t
t
Symbol
IRI - FAST
IG - FAST
IF - FAST
t
t
t
t
RAZ
t
RDA
IRW
IDM
t
t
t
t
RA
IRI
IW
IG
IF
Typical
1.5T
1.5T
Min
16T
63T
18T
14T
18T
14T
22T
18T
22T
18T
—
Typical
Max
64T
21
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2
See Figure
21
T.
10-5
10-5
10-5
10-6
10-7
10-7
10-8
10-9
10-9
Preliminary