MC56F8346MFVE Freescale Semiconductor, MC56F8346MFVE Datasheet - Page 22
![IC DSP 16BIT 60MHZ 144-LQFP](/photos/12/21/122157/mc56f8346mfve_sml.jpg)
MC56F8346MFVE
Manufacturer Part Number
MC56F8346MFVE
Description
IC DSP 16BIT 60MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet
1.MC56F8346VFVE.pdf
(178 pages)
Specifications of MC56F8346MFVE
Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
62
Program Memory Size
136KB (68K x 16)
Program Memory Type
FLASH
Ram Size
6K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Data Bus Width
16 bit
Processor Series
MC56F83xx
Core
56800E
Numeric And Arithmetic Format
Fixed-Point
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
62
Data Ram Size
4 KB
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Interface Type
SCI, SPI, CAN
Minimum Operating Temperature
- 40 C
For Use With
MC56F8367EVME - EVAL BOARD FOR MC56F83X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8346MFVE
Manufacturer:
Freescale
Quantity:
42
Company:
Part Number:
MC56F8346MFVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC56F8346MFVE
Manufacturer:
FREESCALE
Quantity:
20 000
22
Signal Name
(GPIOA10)
(GPIOA11)
(GPIOA12)
(GPIOA13)
(GPIOA8)
(GPIOA9)
CLKO
A0
A1
A2
A3
A4
A5
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Pin No.
138
10
11
12
13
14
3
Output
Output
Output
Input/
Type
disabled,
pull-up is
output is
disabled
output is
In reset,
In reset,
enabled
During
56F8346 Technical Data, Rev. 15
Reset
State
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test purposes.
See
Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0 - A5 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
Part 6.5.7
for details.
Signal Description
Freescale Semiconductor
Preliminary