DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 208
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 208 of 1049
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Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode
or single address mode.
This bit is invalid in full address mode.
Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is
performed, of the internal interrupt source selected by the data transfer factor setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared
automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer
factor setting does not issue an interrupt request to the CPU or DTC.
When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a
transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source
should be cleared by the CPU or DTC transfer.
When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the
CPU or DTC regardless of the DTA bit setting.
Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of
the internal interrupt source selected by the channel 1B data transfer factor setting.
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of
the internal interrupt source selected by the channel 1A data transfer factor setting.
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the
internal interrupt source selected by the channel 0B data transfer factor setting.
Rev.6.00 Oct.28.2004 page 178 of 1016
REJ09B0138-0600H
Bit 12
SAE0
0
1
Bit 11
DTA1B
0
1
Bit 10
DTA1A
0
1
Bit 9
DTA0B
0
1
Description
Transfer in dual address mode
Transfer in single address mode
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
Clearing of selected internal interrupt source at time of DMA transfer is enabled
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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