DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 507
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous
mode, causing abnormal termination.
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is
sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode,
MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
Bit 3
PER
0
1
Bit 2
TEND
0
1
Bit 1
MPB
0
1
Description
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does not
match the parity setting (even or odd) specified by the O/E bit in SMR*
Description
[Clearing conditions]
[Setting conditions]
Description
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
Rev.6.00 Oct.28.2004 page 477 of 1016
2
(Initial value)*
(Initial value)*
(Initial value)
REJ09B0138-0600H
1
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