DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 269
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 269 of 1049
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(b) Write Data Buffer Function and DMAC Operation Timing
The DMAC can start its next operation during external access using the write data buffer function. Consequently, the
DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function
is disabled. Also, internal bus cycles maybe hidden, and not visible.
(c) Write Data Buffer Function and TEND Output
A low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an
internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level
may not be output from the TEND pin if the write data buffer function is used when data transfer is performed between an
internal I/O register and on-chip memory.
If at least one of the DMAC transfer addresses is an external address, a low level is output from the TEND pin.
Figure 7-42 shows an example in which a low level is not output at the TEND pin.
Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with
DMAC internal operations. The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed
by detection of a low level.
Activation Source Acceptance: At the start of activation source acceptance, a low level is detected in both DREQ pin
falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected.
Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the
DMABCRL write to enable transfer.
Internal write signal
Internal read signal
External address
Figure 7-42 Example in Which Low Level is Not Output at TEND Pin
Internal address
HWR, LWR
TEND
ø
External write by CPU, etc.
Not output
DMA
read
Rev.6.00 Oct.28.2004 page 239 of 1016
DMA
write
REJ09B0138-0600H
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