DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 387
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 387 of 1049
- Download datasheet (5Mb)
Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0)
IOA3 to IOA0 specify the function of TGRA.
IOC3 to IOC0 specify the function of TGRC.
Note:
*
When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
Channel
0
Channel
0
I/O Control C3 to C0 (IOC3 to IOC0):
Bit 3
IOA3
0
1
Bit 3
IOC3
0
1
Bit 2
IOA2
0
1
0
1
Bit 2
IOC2
0
1
0
1
Bit 1
IOA1
0
1
0
1
0
1
Bit 1
IOC1
0
1
0
1
0
1
Bit 0
IOA0 Description
0
1
0
1
0
1
0
1
0
1
Bit 0
IOC0 Description
0
1
0
1
0
1
0
1
0
1
TGR0A is Output disabled
output
compare
register
TGR0A is
input
capture
register
TGR0C is Output disabled
output
compare
register*
TGR0C is
input
capture
register*
1
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCA0 pin
Capture input
source is channel
1/ count clock
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1
count-up/count-down
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1
count-up/count-down
Rev.6.00 Oct.28.2004 page 357 of 1016
(Initial value)
(Initial value)
REJ09B0138-0600H
: Don’t care
: Don’t care
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