EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 129

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

DS785UM1
The normal boot function is described in
Serial boot is functionally identical to normal boot except that the SBoot bit in the SysCfg
register is set. This mode is available for a software configuration option that is readable by
the boot code.
In either normal boot or serial boot mode, once the processor starts up, it will begin to
execute the instruction at logical address 0x0000_0000. Various configuration options are
provided to select a memory device for booting from at address location 0. The options are
listed in
EECLK EEDAT BOOT1
0
0
1
1
1
1
Table
1
1
1
1
1
1
5-2.
0
0
0
0
0
0
BOOT0 ASDO CSn[7:6]
Copyright 2007 Cirrus Logic
0
0
1
0
0
0
Table 5-2. Boot Configuration Options
1
0
1
0
x
x
Chapter 4 on page
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
xx
xx
External boot fusing Sync boot mode and SDCSn3.
The media type must be either SROM or SyncFLASH.
The selection of the bus width is determined by latched
CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
External boot using Async boot mode and CSn0. The
selection of the bus width is determined by latched
CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
Internal boot from UART1.
Internal SPI boot if HeaderID is found.
Internal boot using Sync boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
See memory map in
boot mode.
Internal boot using Async boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
See memory map in
ASYNC boot mode.
4-1.
Boot Configuration
Table 2-7 on page 2-16
Table 2-7 on page 2-16
EP93xx User’s Guide
System Controller
for SYNC
for
5-3
5