EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 412

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

10
10-18
DMA Controller
EP93xx User’s Guide
10.1.11.2 Hardware-Initiated M2M Transfers
10.1.12 Buffer Descriptors
At the start of a receive or transmit data transfer, the AHB Master Interface uses the low order
4 bits of the current DMA address to decide on the data transfer size to use. If the low-order 4
bits are zero, the first transfer is a quad word access. If they are not all zero, then if the low-
order two bits are zero, then the first transfer is a word transfer. Word transfers will continue,
and the current address incremented each time by one word, until the low-order address bits
indicate that the address is quad-word aligned. If the start address is not word aligned, then
the first transfer is a byte transfer, and the current address is incremented by one byte each
time until the current address is word aligned. Transfers will then be performed as word
transfers until the address is quad-word aligned. (Unless the address becomes quad-word
aligned immediately, in which case quad word transfers are used). Note that in the case of
the M2M channels, source address alignment takes precedence over destination address
alignment. This means that if the source is aligned on a quad-word boundary and the
destination address is aligned on a byte boundary, the channel will burst data into the data
bay and then perform byte transfers to the destination.
The maximum transfer count can be any arbitrary number of bytes.
The DMA Controller transfers data when it owns the AHB bus. Note that with byte/
word/quad-word scheme that the DMA Controller employs, it can never burst across a 1KB
boundary. The reason is that the DMA Controller only bursts when the 4 LSB Address bits are
0000b. A 1 KB boundary has the LSB 10 Address bits being zero. (ref: ARM AMBA
Specification).
The data transfer size for DMA transfers to/from external devices or SSP/IDE is dictated by
the peripheral width. For byte, half-word or word wide peripherals, the DMA is programmed,
using the PW bits of a channels control register, to request byte, half-word or word wide
transfers respectively. Each external device request generates one peripheral width DMA
transfer. If the memory involved is narrower than the peripheral then multiple memory
accesses may be needed, for example, a word wide peripheral transferring to byte wide
memory requires 4 memory transfers. The memory controller handles the generation of
multiple memory accesses if necessary (and not the DMA).
A “buffer” refers to the area in system memory that is characterized by a buffer descriptor,
that is, a start address and the length of the buffer in bytes.
Current DMA Addr Bits [3:0]
xx01, xx10, xx11
0100,1000,1100
0000
Table 10-1. Data Transfer Size
Copyright 2007 Cirrus Logic
Quad-Word access (unless there are less than 4 word
addresses remaining)
Transfer Type
Word access
Byte access
DS785UM1