EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 234

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

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Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
DHORZ:
EQUSER:
INTRLC:
INT:
INTEN:
PIFEN:
Copyright 2007 Cirrus Logic
Double Horizontal - Read/Write
Writing DHORZ = ‘1’ forces the values of the defined bit-
fields in the HClkTotal, HSyncStrtStop, HActiveStrtStop,
HBlankStrtStop, and
(2X programmed value) when used.
0 - Disable
1 - Enable
Equalization/Serration - Read/Write
If SYNCEN = ‘1’ and CSYNC = ‘1’ (both defined below),
writing EQUSER = ‘1’ forces equalization and serration
pulses to be inserted into the composite synchronization
signal on the V_CSYNC pin.
0 - Disable
1 - Enable
Interlace - Read/Write
Writing INTRLC = ‘1’ enables interlaced frame timing.
0 - Disable
1 - Enable
Interrupt - Read/Write
If INTEN = ‘1’, an INT = ‘1’ status indicates that the end of
active video interrupt has occurred.
0 - No interrupt
1 - Interrupt occurred
Write “0” to clear, write “1” to test.
Interrupt Enable - Read/Write
Writing INTEN = ‘1’ enables the end of active video
interrupt.
0 - Disable
1 - Enable
Parallel Interface Enable - Read/Write
0 - Enable interface for normal display operation
1 - Enable interface for Smart Panel operation
Writing PIFEN = ‘1’ redefines the signals on these pins for
Smart Panel operation:
HClkStrtStop
registers to be doubled
DS785UM1