EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 536

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

14
14-14
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14.4.8 DMA
14.4.9 Writing Configuration Registers
14.5 UART1 Package Dependency
The DMA engine may be used with the UART when transmitting and receiving HDLC
packets. The transmit and receive channels may operate completely independently.
When receiving data in HDLC mode, the DMA channel reads the packet data byte by byte
from the RX FIFO. When it reads the final byte, the HDLC RFC interrupt will occur if enabled.
However, the DMA channel, which buffers the data, may not write all of the data to memory.
To insure that the DMA channel dumps the data, the interrupt handling routine must do the
following:
An extra byte will be read from the UART by the DMA channel. It should be ignored.
Note that if the DMAERR bit in the UART1DMACtrl register is set and the HDLC receiver is in
asynchronous mode, if the receiver sees a break, parity, or framing error, it will indicate an
error condition via RxEnd on the DMA channel.
It is assumed that various configuration registers for the UART/HDLC are not written more
than once in quick succession, in order to insure proper synchronization of configuration
information across the implementation. Such registers include UART1Ctrl and
UART1LinCtrlHigh as well as UART1HDLCCtrl, UART1HDLCAddMtchVal,
UART1HDLCAddMask. These registers should not change often in typical use.
The simplest way to fulfill this requirement with respect to writing the UART1Ctrl and
UART1HDLCCtrl registers is to insure that the HDLC transmitter is enabled before the UART
transmit logic. This will ensure that the UART does not transmit incorrect characters or
unexpectedly transmit characters with UART framing,
First the UART1HDLCCtrl register should be written, setting the TXE bit. Then the UART1Ctrl
register should be written, setting the UARTE bit. In between the two writes, at least two
UARTCLK periods must occur. Under worst case conditions, at least 55 HCLK periods must
separate the two writes. The simplest way to due this is separate the two writes by 55 NOPs.
UART1 uses package pins RXD0, TXD0, CTSn, DSRn, DTRn, RTSn, EGPIO[3], and
EGPIO[0], which are described in
1. Note the values in the MAXCNTx and REMAIN registers for the DMA channel. The
2. Temporarily disable the UART DMA RX interface by clearing the RXDMAE bit in the
3. Wait until the difference between the CURRENTx and BASEx registers in the DMA
difference is the number of bytes read from the UART, which is the size of the HDLC
packet. Call this difference N. Note that the BC field of the UART1HDLCRXInfoBuf
register should also be N.
UART1DMACtrl register.
channel is equal to N + 1.
Copyright 2007 Cirrus Logic
Table
14-4.
DS785UM1