MCL908QY2CDTE Freescale Semiconductor, MCL908QY2CDTE Datasheet - Page 27

• Manufacturer Part Number: MCL908QY2CDTE
• Description: IC MCU 8BIT 1.5K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCL908QY2CDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Freescale Semiconductor
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Addr.
TIM Counter Register High
TIM Counter Register Low
TIM Channel 0 Status and
TIM Channel 1 Status and
Configuration Register 1
Control Register (TSC0)
Control Register (TSC1)
Register High (TMODH)
TIM Status and Control
Register Low (TMODL)
Register High (TCH0H)
Register Name
Register Low (TCH0L)
TIM Counter Modulo
TIM Counter Modulo
Register (TSC)
See page 127.
See page 129.
See page 129.
See page 129.
See page 129.
See page 130.
TIM Channel 0
See page 133.
TIM Channel 0
See page 133.
See page 130.
(CONFIG1)
See page 54.
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
(TCNTH)
(TCNTL)
(1)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
MC68HLC908QY/QT Family Data Sheet, Rev. 3
1. One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits.
2. LVDLVR reset to 0 by a power-on reset (POR) only.
COPRS
Bit 15
CH0F
Bit 15
CH1F
Bit 15
Bit 7
TOF
Bit 7
Bit 7
Bit 7
0
0
0
0
0
1
1
0
0
0
0
= Unimplemented
LVISTOP
CH0IE
CH1IE
Bit 14
Bit 14
Bit 14
TOIE
Bit 6
Bit 6
Bit 6
6
0
0
0
0
1
1
0
0
LVIRSTD
TSTOP
MS0B
Bit 13
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
5
0
1
0
0
1
1
0
0
0
Indeterminate after reset
Indeterminate after reset
LVIPWRD
MS0A
MS1A
TRST
Bit 12
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
R
4
0
0
0
0
0
1
1
0
0
= Reserved
LVDLVR
ELS0B
ELS1B
Bit 11
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
0
3
0
0
0
0
1
1
0
0
(2)
SSREC
ELS0A
ELS1A
Bit 10
Bit 10
Bit 10
U = Unaffected
Bit 2
Bit 2
Bit 2
PS2
Input/Output (I/O) Section
2
0
0
0
0
1
1
0
0
STOP
TOV0
TOV1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
PS1
1
0
0
0
0
1
1
0
0
CH0MAX
CH1MAX
COPD
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PS0
0
0
0
0
1
1
0
0
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