MCL908QY2CDTE Freescale Semiconductor, MCL908QY2CDTE Datasheet - Page 86

• Manufacturer Part Number: MCL908QY2CDTE
• Description: IC MCU 8BIT 1.5K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCL908QY2CDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Low-Voltage Inhibit (LVI)
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.
Clearing the LVI power disable bit (LVIPWRD) enables the LVI to monitor V
reset disable bit (LVIRSTD) enables the LVI module to generate a reset when V
V
mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the LVD trip point voltage. The actual trip
thresholds are specified in
reset.
Once an LVI reset occurs, the MCU remains in reset until V
causes the MCU to exit reset. See
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
10.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module,
and the LVIRSTD bit must be set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
V
continually entering and exiting reset if V
V
10.3.4 LVI Trip Selection
The LVDLVR bit in the configuration register selects whether the LVI is configured for LVD (low voltage
detect) or LVR (low voltage reset) protection. The LVD trip voltage can be used as a low voltage warning.
The LVR trip voltage will commonly be configured as a reset condition since it is very close to the minimum
operating voltage of the device. The LVDLVR bit can be written to anytime so that battery applications
can make use of the LVI as both a warning indicator and to generate a system reset.
86
TRIPF
DD
TRIPF
rises above the rising trip point voltage, V
or V
by the hysteresis voltage, V
DTRIPF
After a power-on reset, the LVI’s default mode of operation is LVR trip
voltage. If a higher trip voltage is desired, the user must set the LVDLVR bit
to raise the trip point to the LVD voltage.
If the user requires the higher trip voltage and sets the LVDLVR bit after
power-on reset while the VDD supply is not above the V
mode, the microcontroller unit (MCU) will immediately go into reset. The
next time the LVI releases the reset, the supply will be above the V
LVD mode.
. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to operate in stop
16.5 DC Electrical
DD
MC68HLC908QY/QT Family Data Sheet, Rev. 3
to remain above the V
DD
HYS
Chapter 13 System Integration Module (SIM)
DD
falls below the V
levels below the V
.
DD
DD
fall below V
is approximately equal to V
Characteristics. Either trip level can be used as a detect or
TRIPR
NOTE
. This prevents a condition in which the MCU is
TRIPF
TRIPF
TRIPF
TRIPF
level. In the configuration register, the
DD
), the LVI will maintain a reset condition until
level, enabling LVI resets allows the LVI
level, software can monitor V
rises above a voltage, V
TRIPR
TRIPF
DD
. V
for LVD
voltage. Clearing the LVI
TRIPR
DD
TRIPR
for the reset recovery
falls below a voltage,
Freescale Semiconductor
is greater than
for
TRIPR
DD
, which
by polling