MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 28

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory Maps
5
5.1
The 56F8006/56F8002 device is based on the 56800E core. It uses a dual Harvard-style architecture with two independent
memory spaces for Data and Program. On-chip RAM is shared by both data and program spaces and flash memory is used only
in program space.
This section provides memory maps for:
On-chip memory sizes for the device are summarized in
Restrictions” column of
5.2
The 56F8006/56F8002 series provide up to 16 KB on-chip flash memory. It primarily accesses through the program memory
buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB. Data can be
read and written to program memory space through primary data memory buses: CDBW for data write and CDBR for data read.
Accessing program memory space over the data memory buses takes longer access time compared to accessing data memory
space. The special MOVE instructions are provided to support these accesses. The benefit is that non time critical constants or
tables can be stored and accessed in program memory.
The program memory map is shown in
28
•
•
Unified RAM (RAM)
On-Chip Memory
1
2
Program Flash
Program address space, including the interrupt vector table
Data address space, including the EOnCE memory and peripheral memory maps
(PFLASH)
All addresses are 16-bit word addresses.
This RAM is shared with data space starting at address X: 0x00 0000; see
Memory Maps
Introduction
Program Map
Begin/End Address
P: 0x1F FFFF
P: 0x00 83FF
P: 0x00 7FFF
P: 0x00 1FFF
P: 0x00 8800
P: 0x00 8000
P: 0x00 2000
P: 0x00 0000
Table
6.
56F8006
8K x 16
1K x 16
Table 7. Program Memory Map
16 KB
2 KB
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
or
or
RESERVED
On-Chip RAM
RESERVED
• Internal program flash: 16 KB
• Interrupt vector table locates from 0x00 0000 to 0x00 0065
• COP reset address = 0x00 0002
• Boot location = 0x00 0000
Table 7
Table 6. Chip Memory Configurations
56F8002
6K x 16
1K x 16
12 KB
2 KB
and
or
or
2
Table
: 2 KB
Table
8.
Erase/program via flash interface unit and word writes to CDBW
6. Flash memories’ restrictions are identified in the “Use
Usable by the program and data memory spaces
Memory Allocation
1
for 56F8006 at Reset
Use Restrictions
Figure
7.
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