MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 78

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupt Vector Table
Appendix A
Interrupt Vector Table
Table 41
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an
interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced
before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral
Reference Manual for detail.
By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
78
Introduction
Section 6.7, “PWM, PDB, PGA, and ADC
Connections,”
Table 12 on page 41
Table 20 on page 45
Table 21 on page 49
Table 25
Table 30 on page 59
Appendix
Table 42 on page 80
Peripheral
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is
and
B on page 80
on page 1
Figure 21 on page 52
on page 37
Number
Vector
Location
2
3
4
5
6
7
9
9
Encoding
User
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
Table 40. Changes Between Revisions 2 and 3
Table 41. Interrupt Vector Table Contents
Priority
Level
Added part marking for devices covered by this document
Updated routing details for ANB24 and ANB25
Removed row about open drain mode (GPIO supports only push-pull mode)
Updated specifications for low-voltage detection threshold (high and low range) and
low-voltage warning threshold
Updated all Supply Current Consumption specifications
Updated ROSC variation over temperature specifications (both ranges)
Removed I
is empty (fast mode and FIFO not supported)
Added note explaining ADC and GPIO naming conventions
For I2C_SMB_CSR, clarified that bits 7 and 6 are reserved
3
3
3
3
3
3
3
3
Vector Base
Address +
2
P:0x0C
C fast mode specifications and footnote about setup time if the TX FIFO
P:0x00
P:0x02
P:0x04
P:0x06
P:0x08
P:0x0A
P:0x0E
P:0x10
P:0x12
Description
Reserved for COP Reset Overlay
EOnCE Transmit Register Empty
Misaligned Long Word Access
EOnCE Receive Register Full
Reserved for Reset Overlay
EOnCE Breakpoint Unit
EOnCE Step Counter
EOnCE Trace Buffer
1
Interrupt Function
HW Stack Overflow
Illegal Instruction
Freescale Semiconductor
2