MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 4

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Block Diagram
2
Figure 1
family are described later in this document. Italics indicate a 56F8002 device parameter.
3
3.1
3.1.1
4
Note: All pins
are muxed with
other peripheral
pins.
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•
•
•
•
•
shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this
Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture
As many as 32 million instructions per second (MIPS) at 32 MHz core frequency
155 basic instructions in conjunction with up to 20 address modes
Single-cycle 16
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
24 Total
Block Diagram
Overview
56F8006/56F8002 Features
Core
2
2
3
2
40
4
6
CMP1
CMP2
Dual GP Timer
ADCA
CMP0
programmable
delay block
ADCB
PGA/ADC
GPIO are
muxed with
all other func
pins.
PWM Outputs
Fault Inputs
GPIOD
CMP
or
16-bit parallel multiplier-accumulator (MAC)
PWM
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
Figure 1. MC56F8006/MC56F8002 Block Diagram
SPI
4
SCI
16 Kbytes flash
12 Kbytes flash
2
Flash Memory
Program RAM
Unified Data /
Memory
Program Controller
2KB
and Hardware
RESET
I
Looping Unit
2
C
2
IPBus Bridge
PAB
CDBR
CDBW
PDB
Watchdog
COP/
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
Generation Unit
Controller
16-Bit 56800E Core
Interrupt
Port or GPIOD
Address
JTAG/EOnCE
4
Integration
Data ALU 16 x 16 + 36
System Bus
System
Module
3
V
Control
Three 16-bit Input Registers
DD
Digital Reg
Four 36-bit Accumulators
Management
Controller
Power
V
3
Low-Voltage
SS
Supervisor
R/W Control
Generator*
V
Clock
Analog Reg
DDA
PIT
Freescale Semiconductor
PMC
V
SSA
ROSC
Oscillator
36-Bit MAC
OSC
Crystal
2
Manipulation
RTC
Unit
Bit