MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 32

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory Maps
5.6
Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56F800E core.
These registers can also be accessed through JTAG port if flash security is not set.
to access or control the EOnCE.
32
X:0xFF FF89 –
X:0xFF FFFB–
X:0xFF FF9F–
X:0xFF FF99–
X:0xFF FF97–
X:0xFF FF95–
X:0xFF FF93–
X:0xFF FF91–
EOnCE Memory Map
X:0xFF FFFF
X:0xFF FFFE
X:0xFF FFFD
X:0xFF FFFC
X:0xFF FF9E
X:0xFF FF9D
X:0xFF FF9C
X:0xFF FF9B
X:0xFF FF9A
X:0xFF FF8E
X:0xFF FF8D
X:0xFF FF8C
X:0xFF FF8B
X:0xFF FF8A
X:0xFF FFA1
X:0xFF FFA0
X:0xFF FF98
X:0xFF FF96
X:0xFF FF94
X:0xFF FF92
X:0xFF FF90
X:0xFF FF8F
X:0xFF FF00
Address
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
Register Acronym
(21–24 bits/stage)
OBMSK (32 bits)
OBAR2 (32 bits)
OTX1/ORX1
OTXRXSR
OTX/ORX
OSCNTR
OBCNTR
(32 bits)
(24 bits)
(24 bits)
(24 bits)
OESCR
OCLSR
OBASE
OTBCR
OTBPR
OBAR1
OBCR
OCR
OSR
OTB
Table 11. EOnCE Memory Map
Transmit and Receive Status and Control Register
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 2
Core Lock/Unlock Status Register
Peripheral Base Address Register
Breakpoint Unit Mask Register 2
Breakpoint Unit Control Register
EOnCE Breakpoint Unit Counter
External Signal Control Register
Transmit Register Upper Word
Receive Register Upper Word
Trace Buffer Control Register
Trace Buffer Pointer Register
Trace Buffer Register Stages
Instruction Step Counter
Transmit Register
Table 11
Receive Register
Control Register
Register Name
Status Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
lists all EOnCE registers necessary
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