MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 7

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
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One serial peripheral interface (SPI)
— Full-duplex operation
— Master and slave modes
— Programmable length transactions (2 to 16 bits)
— Programmable transmit and receive shift order (MSB as first or last bit transmitted)
— Maximum slave module frequency = module clock frequency/2
One inter-integrated Circuit (I
— Operates up to 400 kbps
— Supports master and slave operation
— Supports 10-bit address mode and broadcasting mode
— Supports SMBus, Version 2
One 16-bit programmable interval timer (PIT)
— 16 bit counter with programmable counter modulo
— Interrupt capability
One 16-bit programmable delay block (PDB)
— 16 bit counter with programmable counter modulo and delay time
— Counter is initiated by positive transition of internal or external trigger pulse
— Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input
— Two PDB outputs can be ORed together to schedule two conversions from one input trigger event
— PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control
— Supports continuous or single shot mode
— Bypass mode supported
Computer operating properly (COP)/watchdog timer capable of selecting different clock sources
— Programmable prescaler and timeout period
— Programmable wait, stop, and partial powerdown mode operation
— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
— Choice of clock sources from four sources in support of EN60730 and IEC61508:
Real-timer counter (RTC)
— 8-bit up-counter
— Three software selectable clock sources
— Can signal the device to exit power down mode
Phase lock loop (PLL) provides a high-speed clock to the core and peripherals
— Provides 3x system clock to PWM and dual timer and SCI
— Loss of lock interrupt
— Loss of reference clock interrupt
Clock sources
trigger event
signal for the CMP windowing comparison
– On-chip relaxation oscillator
– External crystal oscillator/external clock source
– System clock (IPBus up to 32 MHz)
– On-chip low power 1 kHz oscillator
– External crystal oscillator/external clock source
– On-chip low-power 1 kHz oscillator
– System bus (IPBus up to 32 MHz)
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
2
C) port
Overview
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