MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 21

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68LK332ACAG16
Manufacturer:
MOTOLOLA
Quantity:
1 045
Part Number:
MC68LK332ACAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
3.2.3 Bus Monitor
3.2.4 Halt Monitor
3.2.5 Spurious Interrupt Monitor
3.2.6 Software Watchdog
SWSR —Software Service Register
MC68332
MC68332TS/D
RESET:
15
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac-
knowledge cycle.
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch-
dog times out and issues a reset. This register can be written at any time, but returns zeros when read.
Register shown with read value
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
Perform a software watchdog service sequence as follows:
a. Write $55 to SWSR.
b. Write $AA to SWSR.
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MODCLK
0
1
8
7
0
0
SWP
1
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
MOTOROLA
$YFFA27
1
0
0
0
0
0
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