MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 76

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68LK332ACAG16
Manufacturer:
MOTOLOLA
Quantity:
1 045
Part Number:
MC68LK332ACAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
HALT — Halt
SPSR — QSPI Status Register
SPIF — QSPI Finished Flag
MODF — Mode Fault Flag
HALTA — Halt Acknowledge Flag
Bit 4 — Not Implemented
CPTQP — Completed Queue Pointer
6.5.3 QSPI RAM
76
MOTOROLA
15
When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can
later be restarted.
SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU
reads this register to obtain status information and writes it to clear status flags.
SPIF is set after execution of the command at the address in ENDQP.
The QSPI asserts MODF when the QSPI is the serial master (MSTR = 1) and the SS input pin is negat-
ed by an external driver.
HALTA is asserted when the QSPI halts in response to CPU assertion of HALT.
CPTQP points to the last command executed. It is updated when the current command is complete.
When the first command in a queue is executing, CPTQP contains either the reset value ($0) or a point-
er to the last command completed in the previous queue.
The QSPI contains an 80-byte block of dual-access static RAM that is used by both the QSPI and the
CPU. The RAM is divided into three segments: receive data, transmit data, and command control data.
Receive data is information received from a serial device external to the MCU. Transmit data is infor-
mation stored by the CPU for transmission to an external peripheral. Command control data is used to
perform the transfer.
Refer to the following illustration of the organization of the RAM.
0 = Halt not enabled
1 = Halt enabled
0 = QSPI not finished
1 = QSPI finished
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the QSPI was enabled
0 = QSPI not halted
1 = QSPI halted
in master mode (SS input taken low).
SPCR3
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
8
SPIF
7
0
RESET:
MODF
6
0
HALTA
5
0
4
0
0
3
0
0
CPTQP
MC68332TS/D
$YFFC1F
0
MC68332
0
0