MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 29

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68LK332ACAG16
Manufacturer:
MOTOLOLA
Quantity:
1 045
Part Number:
MC68LK332ACAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
3.4.11 Misaligned Operands
3.4.12 Operand Transfer Cases
3.5 Chip Selects
MC68332
MC68332TS/D
Byte to 8-Bit Port (Even/Odd)
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)
Word to 16-Bit Port (Aligned)
Word to 16-Bit Port (Misaligned)
3 Byte to 8-Bit Port (Aligned)
3 Byte to 8-Bit Port (Misaligned)
3 Byte to 16-Bit Port (Aligned)
3 Byte to 16-Bit Port (Misaligned)
Long Word to 8-Bit Port (Aligned)
Long Word to 8-Bit Port (Misaligned)
Long Word to 16-Bit Port (Aligned)
Long Word to 16-Bit Port (Misaligned)
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] in-
dicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the
byte offset from the base.
CPU32 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even ad-
dress), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address
is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is
misaligned at an odd address. The CPU32 does not support misaligned operand transfers.
The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU
transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the
first bus cycle and the least significant operand word on a following bus cycle.
The following table summarizes how operands are aligned for various types of transfers. OPn entries
are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1,
SIZ0, and ADDR0 for that bus cycle.
NOTES:
Typical microcontrollers require additional hardware to provide external chip-select signals. Twelve in-
dependently programmable chip selects provide fast two-cycle access to external memory or peripher-
als. Address block sizes of 2 Kbytes to 1 Mbyte can be selected.
1. Operands in parentheses are ignored by the CPU32 during read cycles.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
3. The CPU32 does not support misaligned word or long-word transfers.
Transfer Case
2
Freescale Semiconductor, Inc.
2
3
2, 3
3
For More Information On This Product,
2, 3
3
3
Table 11 Operand Alignment
Go to: www.freescale.com
SIZ1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
SIZ0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
ADDR0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DSACK1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
DSACK0
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
DATA
[15:8]
(OP0)
(OP0)
(OP0)
(OP0)
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
MOTOROLA
DATA
(OP0)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
[7:0]
OP0
OP1
OP0
OP1
OP0
OP1
OP0
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